1. Field of the Invention
The present invention relates to a digital/analog common tuner that can selectively receive digital-modulated television signals and analog-modulated television signals.
2. Description of the Background Art
In the field of broadcasting where the development and use of digitalization continues to advance, analog broadcasting and digital broadcasting are now both available. The demand for a common tuner that can receive both analog/digital broadcast signals has become higher.
The digital broadcast now on air has a channel band identical to that of the conventional analog broadcast (for example, broadcast by the NTSC (National Television System Committee) mode). Therefore, the procedure starting from reception of a signal up to frequency conversion into an intermediate-frequency signal (hereinafter referred to as “IF signal”) can be implemented with one tuner.
FIG. 8 is a functional block diagram to describe the function of the front end (generally represents the operation from signal reception up to demodulation) of a conventional digital/analog common tuner. The digital/analog common tuner 200 shown in FIG. 8 employs the double conversion scheme.
According to the double conversion scheme, the input RF (Radio Frequency) signal is first up-converted into a signal of high frequency (for example, approximately 1200 MHz), and then down-converted into a desired IF signal. The double conversion scheme is advantageous in that superior and stable reception properties can be achieved.
Referring to FIG. 8, digital/analog common tuner 200 includes an RF signal input terminal 201, an RF gain control circuit 202, a first frequency conversion unit with a mixer circuit 203, a local oscillator 204 and a PLL circuit 205, a second frequency conversion unit with a mixer circuit 206, a local oscillator 207 and a PLL circuit 208, and an IF signal output terminal 209. These circuits are accommodated in one cabinet 250 that is shielded electromagnetically.
Digital/analog common tuner 200 further includes an IF signal distribution circuit 211, an analog demodulation unit with an IF-AGC circuit 212, an analog demodulation circuit 213 and an AGC detector circuit 214, a digital demodulation unit with an IF-AGC circuit 215, an A/D converter 216, a digital demodulation circuit 217 and an AGC detector circuit 218, and RF gain control signal buses 219 and 220.
Digital/analog common tuner 200 further includes an RF gain control signal switching circuit 221, a microprocessor 222, a PLL set bus 223, and an RF gain switching signal bus 224.
Digital/analog common tuner 200 additionally includes terminals 225 and 226 to apply respective data and signals on PLL set bus 223 and RF gain switching signal bus 224 into cabinet 250, bandpass filters 231–236 to apply band-filtering at appropriate sites between each of the above-described circuits, and amplifier circuits 237–239 amplifying the level of the signals.
Bandpass filters 231–234 and amplifier circuits 237–239 are also accommodated in cabinet 250.
The operation of digital/analog common tuner 200 will be described schematically here. The RF signal input to RF signal input terminal 201 and filtered by bandpass filter 231 is adjusted to a predetermined signal level by RF gain control circuit 202. The RF signal is amplified by a predetermined level by amplifier circuit 237, and then mixed by mixer circuit 203 of the first frequency conversion unit with a local oscillator signal output from local oscillator 204 under control of PLL circuit 205 to be converted into a first IF signal higher in frequency than the desired IF signal. The first IF signal is filtered by bandpass filter 232, amplified by amplifier circuit 238, filtered again by bandpass filter 233, and then mixed by mixer circuit 206 of the second frequency conversion unit with a local oscillator signal output from local oscillator 207 under control of PLL circuit 208 to be frequency-converted into the desired IF signal. The IF signal is filtered by bandpass filter 234 and amplified by a predetermined level through amplifier circuit 239 to be output to IF signal output terminal 209.
The frequency set data required to convert the frequencies of the first IF signal and the desired IF signal is output from microprocessor 222 onto a PLL set bus 223, and then input into cabinet 250 through terminal 225 to be set at PLL circuits 205 and 208.
The IF signal output from IF signal output terminal 209 is distributed to the system that performs analog demodulation processing and the system that performs digital demodulation processing by an IF signal distribution circuit 211.
In the case of analog broadcast reception, the IF signal is filtered by bandpass filter 235, adjusted to a predetermined signal level by IF-AGC circuit 212, and then demodulated by analog demodulation circuit 213. At this stage, AGC detector circuit 214 provides to IF-AGC circuit 212 a control signal that controls the gain of IF-AGC circuit 212 so that appropriate analog-demodulation is effected, and also outputs, at an RF signal stage, an RF gain control signal onto RF gain control signal bus 219 to control the gain at RF gain control circuit 202.
The RF gain control signal on RF gain control signal bus 219 is provided to RF gain control circuit 202 via RF gain control signal switching circuit 221. At this stage, RF gain control signal switching circuit 221 responds to an RF gain switching signal received from microprocessor 222 via RF gain switching signal bus 224 to select and provide to RF gain control circuit 202 the gain control signal from RF gain control signal bus 219 or 220. Since determination of analog broadcast reception is already made by microprocessor 222 based on the reception channel, and an RF gain switching signal designating selection of RF gain control signal bus 219 is output from microprocessor 222 onto RF gain switching signal bus 224, RF gain control signal switching circuit 221 selects RF gain control signal bus 219 to output the RF gain control signal from AGC detector circuit 214 of the analog demodulation system to RF gain control circuit 202.
In the case of digital broadcast reception, the IF signal is filtered by bandpass filter 236, adjusted to a predetermined level by IF-AGC circuit 215, and then converted into a digital signal by A/D converter 216 to be demodulated by digital demodulation circuit 217. At this stage, AGC detector circuit 218 outputs to IF-AGC circuit 215 a control signal adjusting the gain of IF-AGC circuit 215 so that appropriate digital demodulation is conducted, and also outputs, at the RF signal stage, an RF gain control signal onto RF gain control signal bus 220 to control the gain of RF gain control circuit 202.
The RF gain control signal onto RF gain control signal bus 220 is provided to RF gain control circuit 202 via RF gain control signal switching circuit 221. Since determination of digital broadcast reception is already made by microprocessor 222 based on the reception channel, and an RF gain switching signal designating selection of RF gain control signal bus 220 is output onto RF gain switching signal bus 224 from microprocessor 222, RF gain control signal switching circuit 221 selects RF gain control signal bus 220 to output the RF gain control signal from AGC detector circuit 218 of the digital demodulation system to RF gain control circuit 202.
In digital/analog common tuner 200, IF signal distribution circuit 211 as well as bandpass filter 235, IF-AGC circuit 212, analog demodulation circuit 213 and AGC detector circuit 214 corresponding to the system of analog demodulation processing are circuits that process an analog signal. The signals handled by bandpass filter 236 and IF-AGC circuit 215 of the system that performs digital demodulation processing are also analog signals. Furthermore, RF gain control signal buses 219 and 220 handle analog signals.
In contrast, A/D converter 216, digital demodulation circuit 217, AGC detector circuit 218 and microprocessor 222 are circuits that process digital signals.
Since these circuits are disposed on the same substrate, the analog signal processing circuit vulnerable to noise in digital/analog common tuner 200 will be affected by the noise from the digital signal processing circuit. As a result, various problems such as degradation in the S/N ratio occur.
In a common tuner such as digital/analog common tuner 200, PLL frequency set data used to convert the frequency of a signal and a switching signal used to switch the circuit attribute depending upon the reception of either digital or analog broadcast must be set at predetermined circuits from microprocessor 222. In conventional digital/analog common tuner 200, microprocessor 222 outputs the aforementioned PLL frequency set data and switching signal separately from two I/O ports. However, the requirement of two I/O ports will restrict the microprocessor that can be adopted. If an additional switching signal is required to induce the necessity of more I/O ports, the selection of the microprocessor will be further restricted. This becomes a factor in increasing the cost of the microprocessor.
If the number of buses is increased according to the additionally required I/O ports, restriction will be imposed on the layout on the substrate. Also, the noise generated from the bus through which a digital signal is transmitted may adversely affect the performance of the tuner. Therefore, it is desirable to keep the number of buses as low as possible.